Generally, a memory cell in an SRAM (Static Random Access Memory) includes six elements (6 transistors, or four transistors and 2 resistors). A memory cell for an SRAM using tunneling diode devices has been proposed. This memory cell includes three elements that are two diodes and one transistor so as to be suitable to form memory cells in a high density.
The characteristic of a tunneling diode device highly depends on the characteristic of a tunneling barrier. Therefore, the fluctuation of the barrier size cause the fluctuation of the (tunneling) current which becomes several digits in a process of which a minimum feature size is 10 nm or less. As a result, the achievement of the memory cell becomes difficult in this size regime. In addition, a tunneling diode device that has a size equal to or smaller than a depletion layer width cannot be formed in principle. Therefore, it is quite difficult to form nano-meter order devices.
Conventionally, a transistor using silicon nanowires is proposed.